IRU3073CQTR【PDF 5/21 页】IC REG DL BCK/LINEAR 16-QSOP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录40

1页 2页 3页 4页 [5页]6页 7页 8页 9页

IRU3073

Rev. 1.0

09/17/03

www.irf.com

THEORY OF OPERATION

Introduction

The IRU3073 is designed for a two output application

and it includes one synchronous buck controller and a

linear regulator controller. The PWM section is a fixed

frequency, voltage mode and consists of a precision ref-

erence voltage, an uncommitted error amplifier, an inter-

nal oscillator, a PWM comparator, an internal regulator,

a comparator for current limit, gate drivers, soft-start and

shutdown circuits (see Block Diagram).

The output voltage of the synchronous converter is set

and controlled by the output of the error amplifier; this is

the amplified error signal from the sensed output voltage

and the voltage on non-inverting input of error amplifier(VP).

This voltage is compared to a fixed frequency linear

sawtooth ramp and generates fixed frequency pulses of

variable duty-cycle, which drives the two N-channel ex-

ternal MOSFETs.

The timing of the IC is provided through an internal oscil-

lator circuit which uses on-chip capacitor. The oscilla-

tion frequency is programmable between 200KHz to

400KHz by using an external resistor. Figure 14 shows

switching frequency vs. external resistor (Rt).

Soft-Start

The IRU3073 has a programmable soft-start to control

the output voltage rise and limit the current surge at the

start-up. To ensure correct start-up, the soft-start se-

quence initiates when the input supplies rise above their

threshold and generates the Power On Reset (POR) sig-

nal. Soft-start function operates by sourcing an internal

current to charge an external capacitor to about 3V. Ini-

tially, the soft-start function clamps the E/As output of

the PWM converter and disables the short circuit pro-

tection. During the power up of the buck converter, the

output starts at zero and voltage at Fb1 is below 0.4V.

The feedback UVLO is disabled during this time by in-

jecting a current (64mA) into the Fb1. This generates a

voltage about 1.6V (64mA325K) across the negative

input of E/A and positive input of the feedback UVLO

comparator (see Fig3).

Figure 3 - IRU3073 soft-start diagram.

The magnitude of this current is inversely proportional to

the voltage at soft-start pin.

The 20mA current source starts to charge up the exter-

nal capacitor. In the mean time, the soft-start voltage

ramps up, the current flowing into Fb1 pin starts to de-

crease linearly and so does the voltage at the positive

pin of feedback UVLO comparator and the voltage nega-

tive input of E/A.

When the soft-start capacitor is around 1V, the current

flowing into the Fb1 pin is approximately 32mA. The volt-

age at the positive input of the E/A is approximately:

The E/A will start to operate and the output voltage starts

to increase. As the soft-start capacitor voltage contin-

ues to go up, the current flowing into the Fb1 pin will

keep decreasing. Because the voltage at pin of E/A is

regulated to reference voltage 0.8V, the voltage at the

Fb1 is:

32mA325K = 0.8V

VFB1 = 0.8-25K3(Injected Current)

20uA

64uA

Max

POR

Error Amp

64uA325K=1.6V

When SS=0

POR

0.4V

Feeback

UVLO Comp

SS/SD

Fb1

Comp

25K

0.8V

25K

HDrv

LDrv

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式